1. Field of the Invention
The present invention relates to a semiconductor memory device which rewritably stores data in a memory cell array divided into unit blocks, and particularly relates to a semiconductor memory device having a configuration of storing data of the unit blocks in a cache memory.
2. Description of the Related Art
Generally, a semiconductor memory device such as a DRAM has a configuration in which a memory cell array is divided into a plurality of banks and each bank is further divided into a plurality of unit blocks. Data is stored in a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines in each unit block. For example, a row of sense amplifiers including a plurality of sense amplifiers is generally arranged on each of both sides of the unit block. Further, a configuration in which switches are provided between each unit block and each row of sense amplifiers has been also proposed (see, for example, Japanese Patent Laid-Open No. 2004-103657). Thus, by configuring the row of sense amplifiers arranged for each unit block, data of the memory cells can be stored in the cache memory every time when an arbitrary word line is selected and activated. That is, the row of sense amplifiers can be used as the cache memory (hereinafter referred to as “sense amplifiers cash”).
Generally, refresh operation needs to be performed at a predetermined time interval in order to hold data stored in the DRAM. This refresh operation is controlled so that after bit lines in the unit block to be refreshed are pre-charged, a predetermined word line is selected and activated, and data read from memory cells on the selected word line is amplified by the sense amplifiers and is rewritten into the memory cells. In this case, when the row of sense amplifiers attached to the unit block is being used as a sense amplifiers cache, the stored data in the sense amplifiers cache at that time is destroyed in the refresh operation. Therefore, a time in which data can be held in the sense amplifiers cache is under restriction of a refresh interval. Usually, in the DRAM, data in the sense amplifiers cache needs to be updated each time the refresh operation is performed, and the refresh operation is performed at a short interval of some microseconds. As a consequence, it is a problem that the sense amplifiers cache cannot be used effectively.
Meanwhile, a configuration having a special purpose cache memory provided separately from the memory cell array can be employed. By such a configuration, data in the cache memory is not destroyed, and thus the refresh operation does not have the above mentioned restriction. However, it is improper to provide the special purpose cache memory for each unit block in viewpoints of cost and chip area, and it is not realistic to use a common cache memory for a large number of unit blocks because of complexity in control and configuration for data transfer.